Traditionally, logic verification that is done on cycle-based simulators plays an important role in the process of chip development. Currently available cycle-based simulators may be categorized into two classes: event-driven work-station based simulation software and specially designed hardware simulation acceleration engine. The pure software approach is inefficient for larger verification targets because of software overhead and slow inter-workstation communication links. Existing hardware simulation acceleration engines are not just expensive to construct and maintain, but they are also inefficient in the sense that they do not utilize the intrinsic characteristic of hardware behavior—data-driven execution.
Current verification technology is mostly based on the field-programmable gate arrays (FPGAs), a cluster of personal computers (PCs), or specially designed application-specific integrated circuit (ASIC) systems. As is known in the art, FPGAs may be used to implement any logical function that an ASIC could perform, but the ability to update the functionality after shipping offers advantages for many applications. Current FPGA based verification technologies usually try to directly map target logic into a group of FPGAs and emulate a target system. This approach is not scalable and can become extremely expensive in constructing FPGAs as the complexity of the target logic increases. Also, the synthesizing processes normally take a long time, which makes this approach very inefficient at the early stages of the chip logic development when design changes occur very often. Furthermore, FPGAs are intrinsically much slower than custom designed circuits.
An alternative verification technology may use a cluster of personal computers (PCs). The biggest problem associated with simulating complex chip logic on a PC cluster is low performance. Hindering factors in using the PC cluster may come from bad instruction and data cache locality, inefficient communication channel, and operating system overhead.
Another alternative verification technology may use ASIC systems. For example, some big companies have developed dedicated logic simulation machines with specially designed ASICs to accelerate the logic simulation process. These systems are usually extremely expensive to develop and upgrade, and they are less programmable than other types of systems. The existing machines are also rarely commercially available to outside users.